In this article, we will introduce you to VHDL and Verilog. We will also study the basic structure of a Verilog module and get familiar with the Verilog ‘wire’ data type and its vector form. We will also tell you the basic difference between Verilog and VHDL.
What is Verilog?
Verilog is a type of Hardware Description Language (HDL), standardized as IEEE 1364. It is most commonly used in describing electronic circuits and systems, used in the design and verification of digital circuits.
What is VHDL?
VHDL is also a type of Hardware Description Language (HDL) used in electronic design automation to describe the behavior and structure of electronic systems and is particularly suited as a language to describe the structure and behavior of digital electronic hardware designs as well as conventional digital circuits.
Do I Need Both Verilog and VHDL?
Before we continue, let us discuss whether we require both these languages? Both of them are powerful tools used in designing complex digital circuits, but you’re free to master one that you wish to use. You should, however, have a basic understanding of both languages.
The Evolution of Verilog
Verilog was designed in 1984 at Gateway Design Automation. In 1987, VHDL became an IEEE standard while Verilog made it into the scene by 1995. Today both these are powerful HDLs (Hardware Description Languages). The word ‘Verilog’ is derived from the words ‘verification’ and ‘logic’. This is because the language was first to be used as a simulation and verification tool.
Now we will discuss some Verilog concepts.
In this example, let us write the Verilog code for the circuit shown below.
There are two inputs and one output is shown and the ports are one bit wide. The circuit shows an AND function from the two inputs resulting in an output at the out1 port. The Verilog description can be shown as:
Lines 1 and 8:
The keywords ‘module’ and ‘endmodule’ are used to specify the lines in between them that describe the Circuit_1.
Lines 2 to 6:
These lines are specifying the interface of ‘Circuit_1’ with its environment. The keywords ‘input’ and ‘output’ show the input and output ports. After this the keyword ‘wire’ specifies a Verilog data type which represents a physical wire in the design. There are three wires a, b and out1 in our module.
The line describes the AND functionality of the circuit with the bitwise AND operator ‘&’. The keyword ‘assign; is used to put a & b on the output port. This is also known as a continuous assignment because it is always active whenever the expression changes on the right hand side, the left hand side is re-evaluated i.e. its output is continuously updating.
Comparing Example 1 with the VHDL Code:
The Figure below shows the Verilog and VHDL descriptions for the Circuit_1 module.
In VHDL we must include some libraries which define the data types and operators. Therefore the VHDL code is more descriptive. However, in some cases this is advantageous as in the modeling of higher-level systems.
Four-Value System of Verilog:
There are four values used in Verilog data types:
- 0: low logic/false
- 1: high logic/true
- z: for the high-impedance state (also used to describe the output of a tri-state buffer)
- x: unknown value
The VHDL std_logic data type can take on nine different values but commonly used values are ‘0’, ‘1’, ‘Z’, and ‘-’ (‘-’ denotes an unknown value).
In the next example, let us write the Verilog code for the circuit (Circuit_2) shown in the Figure below.
The following Verilog code describes the shown circuit:
The elements used are similar to those in our previous example, however, an internal signal is defined in line 10. The keyword ‘wire’ specifies the data type of this connection. The bitwise operator ‘~’ is used for NOT and ‘|’ for OR operations. The bitwise operator ‘^’ is used for XOR operation.
The following figure will show both the Verilog and VHDL descriptions for the Circuit_2 module so you can observe the differences.
For our third and final example, we will give the Verilog code for the schematic shown in the following figure: You will notice the red and blue input ports are combined with the AND operator. The result is shown by the output port. We can group the signals and treat them as a vector which will make our code compact and readable. We can describe the above circuit by using the Verilog code. We can also easily extend the code from Listing 1 to describe this circuit.
Keep in mind that the index range of the vectors can be ascending as shown ([0:2]) or descending ([2:0]). The descending format is usually less prone to error and can be used instead.